FIG. 9 shows an example of an image reading device. The image reading device is configured such that a control board 100 is connected to a reading sensor 101, such as CCD, through a harness 102. The control board 100 has a clock generating circuit 103 to generate a reference clock generated. The reference clock is input to an ASIC 104 disposed on the control board 100. The ASIC 104 generates, based on the reference clock, a sensor driving signal that is used for controlling the read timing of the reading sensor 101, and transmits the generated sensor driving signal to the reading sensor 101 through the harness 102.
The reading sensor 101 reads a document line by line on the basis of the sensor driving signal, and transmits the acquired analog read image signal to an analog front end (AFE) 105 on the control board 100 through the harness 102. The AFE 105 A/D-converts the received read image signal on the basis of the clock signal input from the ASIC 104 to generate digital reading data, and transfers the reading data to the ASIC 104. The ASIC 104 executes various image processes on the reading data.
The image reading device employs a single reference clock, on the basis of which components operates for synchronization. However, in order to efficiently drive circuits for performing various system control operations, such as an image process on the reading data and a control process of the motor for moving the reading sensor relative to the document, it is required to use reference clocks suitable for system configurations or CPU characteristics. In order to reduce the electromagnetic interference (EMI), the use of a clock generating circuit (such as an SSCG) having a function of modulating the frequency of the reference clock is also considered.
In this connection, Japanese Patent Unexamined Publication No. 2001-238043 discloses an image reading device designed to reduce EMI noise. The image reading device includes a clock generator (6A) for generating a clock (15.0 MHz) for processing data of odd-line-numbered pixels and a clock generator (6B) for generating a clock (15.3 MHz) for processing data of even-line-numbered pixels. The clock of 15.3 MHz is supplied to the input side of a buffer (4), whereas the clock of 15.0 MHz is supplied to the output side of the buffer (4). Accordingly, data of even-numbered pixels are written in the buffer (4) at 15.3 MHz and read therefrom at 15.0 MHz so that data of odd-line-numbered pixels and data of even-line-numbered pixels are synchronized and supplied to a multiplexer (5). Because an A/D converter (3A) operates at 15.0 MHz for processing the odd-line-numbered pixel data and an A/D converter (3B) operates at 15.3 MHz for processing the even-line-numbered pixel data, EMI noise from the A/D converter (3A) and EMI noise from the A/D converter (3B) are not superimposed one on another. Accordingly, the image reading device can effectively reduce EMI noise generated therefrom.
On the other hand, the reading sensor is required to operate at a reference clock optimal for the characteristics thereof in order to increase reading speed thereof. However, it is difficult to obtain the optimal clock optimal based on a reference clock used in the system.
Even in the case of the image reading device disclosed in Japanese Patent Unexamined Publication No. 2001-238043, a CCD (2) operates based on 15.0 MHz to read pixels on an odd-numbered line and based on 15.3 Mhz to read pixels on an even-numbered line, and thus is bound to the clocks of the generators (3A,3B).